This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2000-27911, filed on Feb. 4, 2000, the entire contents of which are incorporated by reference herein.
The present invention relates generally to a memory-consolidated image processing LSI (Large Scale Integrated circuit). More specifically, the invention relates to a memory-consolidated image processing LSI capable of being driven at low power consumption. Memory elements consolidated with an image processing part to constitute a memory part include ferroelectric random access memories (FeRAMs), magneto-resistance random access memories (MRAMs) and so forth.
Conventional memory consolidated image processing LSIs are designed to improve the processing speed for writing or the like, and have been scarcely taken measures to cope with the decrease of the driving power of the LSIs.
In order to access the memory part of the memory consolidated image processing LSI, a first power A is first consumed to access the page regions of the storage region of a memory, which comprises a plurality of page regions including a plurality of word regions, and then, a second power B is consumed to access the word regions. For example, referring to FIGS. 1A and 1B, the principle of storage in a conventional memory consolidated image processing LSI for storing image information will be described below. In FIGS. 1A and 1B, as an example of a consolidated memory, a DRAM will be described.
FIG. 1A shows a display screen S of a display unit, such as a CRT (Cathode Ray Tube) or a liquid crystal display, for displaying, e.g., dynamic image data. The display screen S is virtually segmented into a plurality of page regions P. Each of the page regions P comprises a plurality of words L, each of which is, e.g., data for one line scanned in a horizontal scanning period (1H). The data thus virtually segmented on the display screen are stored in a storage region M of the DRAM shown in FIG. 1B. The storage region M comprises a plurality of storage regions P, which correspond to the display screen S, for storing data for one line, and a plurality of word storage regions L, each of which corresponds to data for 1 H to be included in a corresponding one of the storage regions P.
Thus, the conventional memory consolidated image processing LSI is designed to store image data for one frame on the display screen S and data stored in the DRAM so that the image data correspond to the data stored in the DRAM. For that reason, in order to access the DRAM, after the storage region P for each page shown in FIG. 1B is accessed, each word L corresponding to a scanning line is accessed to write or read data.
Therefore, when data for a few pages must be read in order to carry out a process, such as a motion compensation, with respect to dynamic image data, the power A for accessing the pages must be multiplied by the number of the pages (Pxc3x97n timesxc3x97power A), and the power B for accessing the words must be multiplied by the number of required words (Lxc3x97m timesxc3x97power B). Therefore, the whole power consumption increases in proportion to the numbers of accessed pages and words. As a result, if the region of an image, which is required to be processed, extends over a large number of pages, the power consumption for the pages is required.
Also in image processing LSIs utilizing external memories other than the above described conventional memory consolidated image processing LSIs, a technique called tiling is used for reducing the number of accesses to a DRAM to shorten the access time. The tiling is designed to change the reading sequence of data on a display screen S although it does not change the image range. For example, the tiling takes account of the fact that the reading time is shorten by simultaneously reading two word data on the same page, wherein word data stored in another page exists therebetween, when the two word data are intended to be read. However, since the access speed is improved as the sizes of a page and a word region increase, a larger page size and a larger word size are used. However, when an external memory is utilized, the degree of freedom capable of selecting the sizes of a page and a word is small.
As described above, according to the conventional memory consolidated image processing LSIs, when a memory is accessed to cut out desired image data, excessive page regions are first accessed, and then, a desired word of the words stored therein is accessed, so that there is a problem in that vast amounts of power must be consumed when data to be acquired extends over a few pages.
In addition, memory consolidated image processing LSIs mounted on portable electronics are often driven by a rechargeable battery. Although the loaded battery may have a large charging capacity so that the LSIs can be used for a long time, this prevents the whole electronics from being miniaturized since the weight increases. Therefore, although the capacity of the loaded battery is determined in view of the weight and size to some extent, it has been requested that the power consumption of the LSI should be saved as small as possible.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a memory consolidated image processing LSI capable of accomplishing an efficient power consumption by reducing a first power consumption for accessing a page by the device that the LSI has a size and shape by which an image processing can be most efficiently carried out with respect to the way to segment one of pages constituting a screen when a DRAM is accessed.
In order to accomplish the aforementioned and other objects, according to a first basic construction of the present invention, a memory consolidated image processing LSI comprises: a memory part including a page region for storing image data for a plurality of lattice-like page ranges which are formed by segmenting an image plane corresponding to a display screen and each of which has sides a power of 2 long, and word regions, each of which stores image data for a plurality of word ranges formed by segmenting each of the page ranges and which are assembled to constitute the page region; and an image access part for word-accessing the word ranges after accessing the page ranges by a pre-charge in order to access the memory part. The page region or word region stored in said memory part is set so as to have a multiplied value of a power consumption per one of pre-charges in a power consumption model of a memory by an average number of the pre-charges to be a substantially minimum value, or a multiplied value of a power consumption per one of word accesses in a power consumption model of a memory by an average number of the word accesses to be a substantially minimum value. The substantially minimum value does not mean that the multiplied value completely coincides with the absolutely minimum value, and means that the multiplied value includes proximity values of the minimum value.
According a first aspect of the present invention, in the memory consolidated image processing LSI according to the first basic construction, the page ranges on the image plane wherein image data is stored in the page region of the memory part has a size so that the multiplied value of power consumption per one of the pre-charges in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value.
According to a second aspect of the present invention, in the memory consolidated image processing LSI according to the first basic construction, the word ranges on the image plane wherein image data is stored in the word region of the memory part has a size so that the multiplied value of a power consumption per one of the word accesses in a power consumption model of a memory by an average number of word accesses is the substantially minimum value.
According to a third aspect of the present invention, in the memory consolidated image processing LSI according to the first basic construction, the page ranges on the image plane wherein image data is stored in the page region of the memory part has a size so that the multiplied value of a power consumption per one of the pre-charges in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value, and the word ranges on the image plane wherein image data is stored in the word region of the memory part has a size so that the multiplied value of a power consumption per one of the word accesses in a power consumption model of a memory by an average number of word accesses is the substantially minimum value.
In the memory consolidated image processing LSI according to the first basic construction, the image plane may comprise a plurality of pixels, and the page ranges are formed by segmenting the image plane into rectangular ranges with sides 8 to 16 pixels long or in a rectangular range which has a size approximating to that of the square range and which has an aspect ratio of up to 1:2.
In the memory consolidated image processing LSI with such a construction, a two-dimensional plane, which has been stored in the memory region, may be segmented into square areas having the same capacity as that of the page range or rectangular areas with sides of a ratio of 1:2 to be collectively stored in separate page regions.
In the memory consolidated image processing LSI according to the first basic construction, the image plane may comprise a plurality of pixels, and the word ranges may be formed by segmenting the image plane into rectangular ranges with sides 8 to 16 pixels long or in a rectangular range which has a size approximating to that of the square range and which has an aspect ratio of up to 1:2.
In the memory consolidated image processing LSI with such a construction, a two-dimensional plane, which has been stored in the memory region, may be segmented into square areas having the same capacity as that of the page range or rectangular areas with sides of a ratio of 1:2 to be collectively stored in separate page regions.
In the memory consolidated image processing LSI with the above described construction, the memory part may comprise a dynamic random access memory (DRAM). Alternatively, in the memory consolidated image processing LSI with the above described construction, the memory part may comprise a ferroelectric random access memory (FeRAM). Alternatively, in the memory consolidated image processing LSI with the above described construction, the memory part may comprise a magnetoresistance random access memory (MRAM).
In the memory consolidated image processing LSI according to the first basic construction, the image access part may be a circuit for processing a bit stream based on a dynamic image compressing standard, such as MPEG-4, MPEG-2, MPEG-1 or H.263, and the memory part may be a memory having a unit for the preparation for reading, i.e., a region corresponding to the page region in a DRAM, the size of the page range on the image plane being preferably in the range of from 64 pixels to 512 pixels, or in the range of from 512 pixels to 1024 pixels.
In the memory consolidated image processing LSI according to the first basic construction, the image access part may be a circuit for processing a bit stream based on a dynamic image compressing standard, such as MPEG-4, MPEG-2, MPEG-1 or H.263, and the memory part may be a memory having a unit corresponding to a data bus, i.e., the word region corresponding to a word region in a DRAM, the size of the word range on the image plane being preferably in the range of from 8 pixels to 64 pixels, or in the range of from 64 pixels to 256 pixels.
According to a second basic construction of the present invention, an image processing system having an image compressing and/or expanding unit for compressing and/or expanding image information, includes a memory consolidated image processing LSI comprising: a memory part having a plurality of lattice-like page ranges for storing the image data of the page ranges which are formed by segmenting an image plane corresponding to a display screen and each of which has sides a power of 2 long, and a plurality of word ranges for storing the image data of the word ranges which are formed by segmenting each of the page ranges and which are assembled to constitute each of the page ranges; and an image access part for accessing the word ranges after accessing the page ranges by a pre-charge in order to access the memory part.
In the image processing system according to the second basic construction, each of the page ranges and each of the word ranges in the memory part of the memory consolidated image processing LSI may be set to be a desired page range and a desired word range, which allow desired image data to be accessed at the minimum power consumption by the minimum number of pre-charges and the minimum number of charges.
The image processing system according to the second basic construction may further comprise: a raster converting part for raster-converting the image information; and a processing part for converting the image data, which has been converted by the raster converting part, into data corresponding to the desired page and word ranges, wherein the memory consolidated image processing LSI stores the image data for the desired page and word ranges, which has been converted by the processing part, in the page and word regions of the memory part, and the image access part accesses by word-accessing the desired word region after being pre-charged in the desired page region of the memory part.
The image processing system according to the second basic construction may further comprise: a raster converting part for raster-converting the image information; a temporary memory part for temporarily storing the image data which has been converted by the raster converting part; and a processing part for converting the image data, which has been stored in the temporary memory part, into data corresponding to the desired page and word ranges, wherein the memory consolidated image processing LSI stores the desired page and word ranges, which have been converted by the processing part, in the page and word regions of the memory part, and the image access part accesses the desired word region after being pre-charged in the desired page region of the memory part.
The image processing system according to the second basic construction may further comprise an MPEG processing part for compression-coding image data using an MPEG coding system, wherein the memory consolidated image processing LSI stores the desired page and word ranges for the image data, which has been processed by the MPEG processing part, in the memory part, and the image access part accesses by word-accessing the desired word region after being pre-charged in the desired page range of the memory part.
In the image processing system according to the second basic construction, the image access part may be a circuit for processing a bit stream based on a dynamic image compressing standard, such as MPEG-4, MPEG-2, MPEG-1 or H.263, and the memory part may be a memory having the page region corresponding to the page range serving as a unit for the preparation for reading, the size of the page range on the image plane being preferably in the range of from 64 pixels to 512 pixels.
In the image processing system according to the second basic construction, the image access part may be a circuit for processing a bit stream based on a dynamic image compressing standard, such as MPEG-4, MPEG-2, MPEG-1 or H.263, and the memory part may be a memory having the page region corresponding to the page range serving as a unit for the preparation for reading, the size of the page range on the image plane being preferably in the range of from 512 pixels to 1024 pixels.
In the image processing system according to the second basic construction, the image access part may be a circuit for processing a bit stream based on a dynamic image compressing standard, such as MPEG-4, MPEG-2, MPEG-1 or H.263, and the memory part may be a memory having the word region corresponding to the word range as a unit corresponding to a data bus, the size of the word range on the image plane being preferably in the range of from 8 pixels to 64 pixels.
In the image processing system according to the second basic construction, the image access part may be a circuit for processing a bit stream based on a dynamic image compressing standard, such as MPEG-4, MPEG-2, MPEG-1 or H.263, and the memory part may be a memory having the word region corresponding to the word range as a unit corresponding to a data bus, the size of the word range on the image plane being preferably in the range of from 64 pixels to 256 pixels.
According to a third basic construction of the present invention, there is provided a method for processing image data stored in a memory consolidated image processing LSI, which comprises a memory part for storing predetermined image data and having page regions each storing page ranges so that an image plane corresponding to a display screen is segmented into lattice-like ranges each of which has sides a power of 2 long, and a word regions each storing word ranges which are formed by segmenting the page range on the image plane, and an access part for accessing to the memory part in the manner that a multiplied value of a power consumption per one of pre-charges in a power consumption model of a memory by an average number of the pre-charges is a substantially minimum value and that a multiplied value of a power consumption per one of word accesses in a power consumption model of a memory by an average number of the word accesses is a substantially minimum value, the method comprising: a step of accessing in a first stage by pre-charging to the page region of the memory part in which desired data are stored; a step of accessing in a second stage by ward accessing to the word regions of the memory part in which desired data are stored; a step of reading out the desired data from the memory part; and a step of performing predetermined image processing to image data which are read in the manner that a multiplied value of a power consumption per one of pre-charges in a power consumption model of a memory by an average number of the pre-charges is a substantially minimum value, or a multiplied value of a power consumption per one of word accesses in a power consumption model of a memory by an average number of the word accesses is a substantially minimum value.
In the image data processing method according to the third basic construction, the page region in the memory part is set to have a size so that the multiplied value of the power consumption per one of the pre-charges in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value.
In the image data processing method according to the third basic construction, the word region in the memory part is set to have a size so that the multiplied value of a power consumption per one of word accesses in a power consumption model of a memory by an average number of the word accesses is the substantially minimum value.
In the image data processing method according to the third basic construction, the page region in the memory part is set to have a size so that the multiplied value of the power consumption per one of the pre-charges in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value, and the word region in the memory part is set to have a size so that the multiplied value of a power consumption per one of word accesses in a power consumption model of a memory by an average number of the word accesses is the substantially minimum value.
According to a fourth basic construction of the present invention, there is provided method for designing a memory consolidated image processing LSI, which comprises a memory part for storing predetermined image data, and an access part for accessing the image data stored in the memory part by using two-stage accesses, in which the method comprises: a step of setting a plurality of page ranges so that an image plane corresponding to a display screen is segmented into lattice-like ranges, each of which has sides a power of 2 long, and so that the multiplied value of the power consumption per one of the pre-charges in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value; a step of setting a page region capable of storing the image data for a page range on the image plane in the memory part; a step of setting a plurality of word ranges which are formed by segmenting the page range on the image plane so that the multiplied value of a power consumption per one of word accesses in a power consumption model of a memory by an average number of the word accesses is the substantially minimum value; a step of setting a word region capable of storing the word ranges on the image plane in the page region in the memory part; and a step of storing the image data to be stored by allotting the data into each of the page regions and word regions in the memory part by using a unit of the page ranges and word ranges in the image plane.